A Decomposition Workflow for Integrated Circuit Verification and Validation
A Decomposition Workflow for Integrated Circuit Verification and Validation
复制标题
集成电路验证和确认的分解工作流程
DOI：
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发表时间：
2020
期刊：
影响因子：
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通讯作者：
G. Via
中科院分区：
文献类型：
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作者：
Adam G. Kimura;Jonathan Scholl;James Schaffranek;Matt Sutter;Andrew Elliott;Michael Strizich;G. Via
本文回顾了一个发达的集成电路（IC）分解工作流程，可以利用提取设计文件和先进的验证和验证技术制造的芯片。在这项工作中，一个商业130纳米微控制器是delayered和成像，以重新创建完整的设计堆叠。使用MicroNet的Pix2Net，提取每个层的特征，从而生成GDSII文件，并为要恢复的目标组件设计网表。在微控制器的只读存储器（ROM）阵列和通用串行通信接口（USCI）上执行完整的分解过程，以恢复布局GDSII和电路网表。使用单精度浮点单元（FPU）测试项目将一系列错误类型合并到设计布局中，从而创建一组具有模糊错误的测试项目。一旦提取了每个修改设计的网表，就将正式验证技术应用于每个网表，从而阐明最初插入布局中的错误。然后将提取的网表转换为寄存器传输级（RTL）表示，并使用原始设计验证测试平台进行仿真。
This paper reviews a developed integrated circuit (IC) decomposition workflow that can be leveraged for extracting design files and performing advanced verification and validation techniques on fabricated chips. In this work, a commercial 130-nm microcontroller is delayered and imaged to recreate the full design stack-up. Using MicroNet’s Pix2Net, the features for each layer are extracted allowing a GDSII file to be generated and design netlists for target components to be recovered. The full decomposition process is executed on both the read only memory (ROM) array and universal serial communications interface (USCI) of the microcontroller to recover the layout GDSII and circuit netlist. A single-precision floating point unit (FPU) test article is used to incorporate a spectrum of error types into the design layout, thus creating a set of test articles with obfuscated errors. Once the netlists for each of the modified designs are extracted, formal verification techniques are applied to each netlist, thus illuminating the errors originally inserted into the layout. The extracted netlists are then converted into register transfer level (RTL) representations and simulated with the original design verification testbench.