Synthesis of Cyberphysical Digital-Microfluidic Biochips for Real-Time Quantitative Analysis

Synthesis of Cyberphysical Digital-Microfluidic Biochips for Real-Time Quantitative Analysis
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DOI:
10.1109/tcad.2016.2600626
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发表时间:
2017-05-01
影响因子:
2.9
通讯作者:
Scott, Kristin
Scott, Kristin
中科院分区:
计算机科学3区
文献类型:
--
作者:
Ibrahim, Mohamed;Chakrabarty, Krishnendu;Scott, Kristin

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近年来,在数字微流控生物芯片(DMFB)上进行分子生物检测的研究取得了很大进展。然而,当今的解决方案存在不支持多个样品路径并且不能有效地利用片上可重构器件的缺点。因此,需要不切实际的人工干预来处理基因表达分析的方案。为了克服这个问题,我们首先描述了我们的台式实验研究,以了解基因表达分析及其与生物芯片设计规范的关系。然后,我们介绍了一个集成的框架,定量基因表达分析使用DMFB。拟议框架包括:1)将资源共享规范并入合成流程的空间重新配置技术; 2)基于定量聚合酶链式反应收集和分析传感器数据的交互式固件;以及3)对从固件层接收到的关于协议流程的决定迅速作出响应的实时资源分配方案。该框架与信息物理集成相结合,开发了第一个定量基因表达的设计自动化框架。仿真结果表明,我们的自适应框架有效地利用片上资源,以减少时间的结果,而不牺牲芯片的寿命。
Considerable effort has recently been directed toward the implementation of molecular bioassays on digital-microfluidic biochips (DMFBs). However, today's solutions suffer from the drawback that multiple sample pathways are not supported and on-chip reconfigurable devices are not efficiently exploited. As a result, impractical manual intervention is needed to process protocols for gene-expression analysis. To overcome this problem, we first describe our benchtop experimental studies to understand gene-expression analysis and its relationship to the biochip design specification. We then introduce an integrated framework for quantitative gene-expression analysis using DMFBs. The proposed framework includes: 1) a spatial-reconfiguration technique that incorporates resource-sharing specifications into the synthesis flow; 2) an interactive firmware that collects and analyzes sensor data based on quantitative polymerase chain reaction; and 3) a real-time resource-allocation scheme that responds promptly to decisions about the protocol flow received from the firmware layer. This framework is combined with cyberphysical integration to develop the first design-automation framework for quantitative gene expression. Simulation results show that our adaptive framework efficiently utilizes on-chip resources to reduce time-to-result without sacrificing the chip's lifetime.