Technology and device scaling considerations for CMOS imagers
Technology and device scaling considerations for CMOS imagers
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DOI：
10.1109/16.544384
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发表时间：
1996-12-01
影响因子：
3.1
通讯作者：
Wong, HS
中科院分区：
文献类型：
--
作者：
Wong, HS
本文分析了器件和技术缩放对有源像素CMOS图像传感器的影响。以半导体工业协会（SIA）的技术路线图为指导，我们计算了与CMOS成像器图像传感性能密切相关的器件特性，并强调了CMOS成像器技术可能需要偏离“标准”CMOS技术的领域。分析了缩放对那些与图像传感性能相关的模拟电路性能的影响。我们的分析表明，虽然“标准”CMOS技术在2 - 1μm工艺代可能无需任何工艺改变就能提供足够的成像性能，但要使CMOS在0.5μm及更先进的工艺代实现高质量成像，就需要对制造工艺进行一些修改，并对像素架构进行创新。最后，概述了CMOS成像器研究领域面临的挑战。
This paper presents an analysis of the impact of device and technology scaling on active pixel CMOS image sensors, Using the SIA roadmap as a guideline, we calculate the device characteristics that are germane to the image sensing performance of CMOS imagers, and highlight the areas where the CMOS imager technology may need to depart from ''standard'' CMOS technologies. The impact of scaling on those analog circuit performance that pertain to image sensing performances are analyzed, Our analyses suggest that while ''standard'' CMOS technologies may provide adequate imaging performance at the 2-1 mu m generation without any process change, some modifications to the fabrication process and innovations of the pixel architecture are needed to enable CMOS to perform good quality imaging at the 0.5 mu m technology generation and beyond. Finally, the challenges to the CMOS imager research community are outlined.