A CMOS 0.18μm 64×64 single photon image sensor with in-pixel 11b time-to-digital converter
A CMOS 0.18μm 64×64 single photon image sensor with in-pixel 11b time-to-digital converter
复制标题
DOI：
10.1109/smicnd.2014.6966414
复制
发表时间：
2014-12
期刊：
影响因子：
--
通讯作者：
I. Vornicu;R. Carmona-Galán;Á. Rodríguez-Vázquez
中科院分区：
文献类型：
--
作者：
I. Vornicu;R. Carmona-Galán;Á. Rodríguez-Vázquez
介绍了一种CMOS 64×64单光子雪崩二极管（SPAD）阵列的设计和特性。它的目标是时间分辨成像，特别是3D成像。实现的像素间距为64μm，填充因子为3.5%。该芯片采用0.18μm标准CMOS工艺制作，实现了飞行时间估计和光子计数的双重功能。该成像器具有可编程的时间分辨率，可用于TDC阵列，分辨率从625 ps降至145 ps。最小时间仓的测量精度低于± 1 LSB DNL和1.7LSB INL。整个动态范围内的TDC抖动小于1 LSB。芯片到芯片的工艺变化和温度通过自动校准被丢弃。每个像素上的快速猝灭/恢复电路通过限制雪崩电流来降低功耗。时间门操作也是可能的。
The design and characterization of a CMOS 64×64 single-photon avalanche-diode (SPAD) array with in-pixel 11b time-to-digital converter (TDC) is presented. It is targeted for time-resolved imaging, in particular 3D imaging. The achieved pixel pitch is 64μm with a fill factor of 3.5%. The chip was fabricated in a 0.18μm standard CMOS technology and implements a double functionality: Time-of-Flight estimation and photon counting. The imager features a programmable time resolution for the array of TDCs from 625ps down to 145ps. The measured accuracy of the minimum time bin is lower than ±1LSB DNL and 1.7LSB INL. The TDC jitter over the full dynamic range is less than 1LSB. Die-to-die process variation and temperature are discarded by auto-calibration. Fast quenching/restore circuit on each pixel lowers the power consumption by limiting the avalanche currents. Time gatedoperation is possible as well.