A 15 GSa/s, 1.5 GHz bandwidth waveform digitizing ASIC
A 15 GSa/s, 1.5 GHz bandwidth waveform digitizing ASIC
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DOI：
10.1016/j.nima.2013.09.042
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发表时间：
2013-09
影响因子：
1.4
通讯作者：
E. Oberla;J. Genat;Hervé Grabas;Henry J. Frisch;Kurtis Nishimura;G. Varner
中科院分区：
文献类型：
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作者：
E. Oberla;J. Genat;Hervé Grabas;Henry J. Frisch;Kurtis Nishimura;G. Varner
PSEC4定制集成电路设计用于记录快速波形，用于大面积飞行时间检测器系统。ASIC采用IBM-8RF 0.13 μ m CMOS工艺制作。在六个模拟通道中的每个通道上，PSEC4采用256采样深度的开关电容阵列（SCA），具有10.5位直流动态范围的斜坡比较ADC，以及具有兴趣区域窗口功能的串行数据读出以减少死区时间。采样率可以在所有通道上的4到15千兆样本/秒（GSa/s）之间进行调整，并通过低抖动延迟锁定环（DLL）在片上进行伺服控制。输入信号在片上被动耦合，模拟带宽为- 3db，为1.5 GHz。静态采样模式下的功耗小于50mw /片；在持续触发和读出速率为50千赫时，芯片输出100毫瓦。在固定模式基座减法后，在750 mV动态范围内，未校正的积分非线性为0.15%。通过线性校正，可以获得完整的1 V信号电压范围。采样时基具有固定模式非线性，有效值为13%，可以进行校正以实现精确的波形特征提取和定时。
The PSEC4 custom integrated circuit was designed for the recording of fast waveforms for use in large-area time-of-flight detector systems. The ASIC has been fabricated using the IBM-8RF 0.13 μ m CMOS process. On each of the six analog channels, PSEC4 employs a switched capacitor array (SCA) of 256 samples deep, a ramp-compare ADC with 10.5 bits of DC dynamic range, and a serial data readout with the capability of region-of-interest windowing to reduce dead time. The sampling rate can be adjusted between 4 and 15 Gigasamples/second (GSa/s) on all channels and is servo-controlled on-chip with a low-jitter delay-locked loop (DLL). The input signals are passively coupled on-chip with a− 3 dB analog bandwidth of 1.5 GHz. The power consumption in quiescent sampling mode is less than 50 mW/chip; at a sustained trigger and a readout rate of 50 kHz the chip draws 100 mW. After fixed-pattern pedestal subtraction, the uncorrected integral non-linearity is 0.15% over a 750 mV dynamic range. With a linearity correction, a full 1 V signal voltage range is available. The sampling timebase has a fixed-pattern non-linearity with an RMS of 13%, which can be corrected for precision waveform feature extraction and timing.