Enabling Stateful Functions for Stream Processing in the Programmable Data Plane
Enabling Stateful Functions for Stream Processing in the Programmable Data Plane
复制标题
在可编程数据平面中启用流处理的有状态函数
DOI：
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发表时间：
2022
期刊：
影响因子：
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通讯作者：
Martin Swany
中科院分区：
文献类型：
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作者：
Sabra Ossen;Lucas R. B. Brasilino;Luke Dalessandro;Martin Swany
传感器丰富的环境是物联网生态系统的重要组成部分，并受益于实时应用。许多应用程序通过对序列数据元素窗口执行连续流处理来对这些物联网工作负载执行实时分析。然而，在服务器CPU上执行轻量级有状态函数会增加高数据速率环境中每个小消息的通信延迟，这主要是由于消息通过复杂的网络堆栈到达CPU。因此，我们提出了一个低延迟和低资源占用的网络功能部署架构，通过引入一个新的计算层。我们提出了一个基于FPGA的交换机/NIC的原型，计算层利用RISC-V软核和高级综合模块。我们在Zynq 7000 FPGA上评估了两个微基准测试的设计，实现了不到10 μs的延迟和不到6%的资源消耗。
Sensor-rich environments are crucial components of the Internet of Things ecosystem and benefit from real-time applications. Many applications perform real-time analytics on these IoT workloads by performing continuous stream processing for a window of sequence data elements. However, executing light-weight stateful functions on server CPUs adds to the communication latency of each small message in a high data rate environment, primarily due to messages traveling through a complex network stack to reach the CPU. Thus, we present an in-network function deployment architecture with low latency and low resource footprint by introducing a new compute layer. We propose an FPGA-based Switch/NIC prototype with a compute layer utilizing RISC-V soft cores and High-Level Synthesis modules. We evaluate the design for two microbenchmarks on a Zynq 7000 FPGA each, achieving less than 10 μs in latency and consuming less than 6 % of resources.