A Timing Yield Model for SRAM Cells at Sub/Near-Threshold Voltages Based on a Compact Drain Current Model
A Timing Yield Model for SRAM Cells at Sub/Near-Threshold Voltages Based on a Compact Drain Current Model
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DOI：
10.1109/tcad.2022.3194812
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发表时间：
2022-02
影响因子：
2.9
通讯作者：
Shan Shen;Peng Cao;Ming Ling;Longxing Shi
中科院分区：
文献类型：
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作者：
Shan Shen;Peng Cao;Ming Ling;Longxing Shi
亚/近阈值静态随机存取存储器（SRAM）设计对于解决功耗受限应用中的内存瓶颈至关重要。然而，高集成密度和工艺变化下的可靠性要求对极小的故障概率进行精确估计。为了在存储电路中捕捉这种“罕见事件”，基于蒙特卡罗（MC）分析的传统模拟的时间和存储开销是不能容忍的。另一方面，由于纳米器件漏极电流（$I_{ds}$）模型的假设分布或过于简化，从物理表达式预测失效概率的经典分析方法在亚/近阈值电压域中变得不准确。本文首先提出了一个简单但有效的经验模型来描述排水诱导的屏障降低（DIBL）效应。在此基础上，推导了SRAM中兴趣度量的概率密度函数。在此基础上，提出了SRAM动态稳定性的两种分析模型，包括存取时间失效和写入失效。所提出的模型可以很容易地扩展到具有不同读/写辅助电路的不同类型的SRAM。在不同的工作电压和温度下，对模型进行了MC模拟验证。在0.5 v $V_{\ maththrm {DD}}$时，访问时间失败模型的平均相对误差仅为8.8%，写失败模型的平均相对误差为10.4%。所需样本数据集的大小比最先进的方法小43.6倍。
Sub/near-threshold static random-access memory (SRAM) design is crucial for addressing the memory bottleneck in power-constrained applications. However, the high integration density and reliability under process variations demand an accurate estimation of extremely small failure probabilities. To capture such a “rare event” in memory circuits, the time and storage overhead of conventional simulations based on the Monte Carlo (MC) analysis cannot be tolerated. On the other hand, classic analytical methods predicting failure probabilities from a physical expression become inaccurate in the sub/near-threshold voltage domain due to the hypothetical distribution or the oversimplified drain current ( $I_{ds}$ ) model for nanoscale devices. This work first proposes a simple but efficient empirical $I_{ds}$ model to describe the drain-induced barrier lowering (DIBL) effect. Based on that, the probability density functions of the interest metrics in SRAM are derived. Two analytical models are then put forward to evaluate SRAM dynamic stabilities, including the access time failure and the write failure. The proposed models can be extended easily to different types of SRAM with different read/write-assist circuits. The models are validated against MC simulations across different operating voltages and temperatures. The average relative errors at 0.5-V $V_{\mathrm{ DD}}$ are only 8.8% for the access-time failure model and 10.4% for the write failure model. The size of the required sample data set is $43.6\times $ smaller than that of the state-of-the-art method.