Summary Part 2 Razor : A Low-Power Pipeline Based on Circuit-Level Timing Speculation
Summary Part 2 Razor : A Low-Power Pipeline Based on Circuit-Level Timing Speculation
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摘要第 2 部分 Razor：基于电路级时序推测的低功耗流水线
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通讯作者：
M. Nath
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作者：
M. Nath
DVS正在成为一种广泛使用的降低高性能处理器能耗的技术。然而，在DVS中选择的允许电压是非常保守的选择，因此即使在最坏的情况下，处理器也能正常工作。据观察，最坏的情况很少发生。因此，有空间更积极地选择允许的电压，即进一步降低它们，以节省更多能源。然而，当最坏的情况确实发生时，这可能会导致计时冲突，从而导致错误的结果。因此，要使这种方法可行，必须在系统中内置一些可靠的错误检测和纠正机制。本文描述了一种这样的电路(Razor FF)，使用它可以检测和纠正错误。这允许积极减少VDD以节省能源。因此，本文讨论了一个重要的问题。
DVS is becoming a widely used technique to reduce the energy consumption of high performance processors. However, the allowable voltages selected in DVS are chosen very conservatively, so that the processor functions correctly even under worst-case conditions. It is observed that the worst-case conditions occur only rarely. Thus, there is room to be more aggressive in selecting the allowed voltages i.e. reducing them further, to save more energy. However, this can lead to timing violations, and hence wrong results, when the worst-case conditions do occur. Thus, for this approach to be feasible, there has to be some reliable error detection and correction mechanism built into the system. This paper describes one such circuit (the Razor FF) using which the errors can be detected and corrected. This allows the aggressive reduction of VDD to save energy. Thus, this paper deals with an important issue.