Platform-Independent Gigabit Communication for Low-Cost FPGAs (Abstract Only)
Platform-Independent Gigabit Communication for Low-Cost FPGAs (Abstract Only)
复制标题
适用于低成本 FPGA 的独立于平台的千兆位通信（仅摘要）
DOI：
10.1145/2684746.2689150
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发表时间：
2015
期刊：
影响因子：
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通讯作者：
Matthias Hinkfoth
中科院分区：
文献类型：
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作者：
Ralf Salomon;Ralf Joost;Matthias Hinkfoth
除其他外，今天可用的现场可编程门阵列(FGA)包含许多用于通信目的的位串行收发器。与诸如正交幅度调制之类的模拟调制方案不同，位串行通信相对容易在数字硬件中实现，因此通常用于FPGA间通信。在这种观点中，只有数据速率和频率限制了电路的带宽。为了克服带宽限制，本研究提出了一种用于数据传输的脉宽调制(PWM)方案。通过调制脉冲的高电压和低电压部分的长度来编码该信息。虽然这种方法并不新鲜，但现有的PWM调制器由于其同步实现性质而具有不令人满意的数据速率。因此，本研究采用异步逻辑实现了调制解调器。其结果是一个概念验证，包括两个TerASIC DE2-70开发板和一条1米同轴电缆。脉宽调制调制解调器的工作频率为333 MHz，脉冲传输周期为3 ns。每个脉冲携带3到4比特的数据。实验结果表明，可实现的数据速率为1千兆比特每秒，这比现场可编程门阵列的手册状态大约50%。
Among other things, field-programmable gate arrays (FPGAs) available today contain numerous bit-serial transceivers for communication purposes. Unlike analog modulation schemes, such as quadrature amplitude modulation, bit-serial communication is relatively easy to implement in digital hardware, and is thus usually used for inter FPGA communication. In this view, only the data rate and frequency limit the bandwidth of the circuit. In order to overcome the bandwidth limit, this research proposes a pulse-width modulation (PWM) scheme for data transmission. The information is coded by modulating the length of the high and low voltage parts of the pulse. Although this approach is not new, existing PWM modulators have unsatisfactorial data rates due to their synchronous implementation nature. Therefore, this research implements both the modulator and demodulator by using asynchronous logic. The result is a proof-of-concept comprising two Terasic DE2-70 development boards and a 1 m coaxial cable. Both the PWM modulator and demodulator run at 333 MHz, and pulses are transmitted every 3 ns. Each pulse carries 3 to 4 bits of data. The experimental results indicate an achievable data rate of one gigabit per second, which is about 50 % larger than the FPGA's handbook states.