Closing the Design Loop: Bayesian Optimization Assisted Hierarchical Analog Layout Synthesis
Closing the Design Loop: Bayesian Optimization Assisted Hierarchical Analog Layout Synthesis
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DOI：
10.1109/dac18072.2020.9218621
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发表时间：
2020-07
期刊：
影响因子：
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通讯作者：
Mingjie Liu;Keren Zhu;Xiyuan Tang;Biying Xu;Wei Shi;Nan Sun;D. Pan
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文献类型：
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作者：
Mingjie Liu;Keren Zhu;Xiyuan Tang;Biying Xu;Wei Shi;Nan Sun;D. Pan
现有的模拟版图合成工具对后期版图性能的保证不足，处理系统级设计的能力有限。在本文中，我们提出了一个闭环分层模拟布局合成器，能够处理系统设计。为了保证系统性能，利用多目标贝叶斯优化的布局后仿真，对构建块布局实现进行了高效优化。据我们所知，这是第一个证明在通用模拟系统设计上自动布局合成成功的工作。实验结果表明，合成的连续时间∆Σ调制器（CTDSM）的后布局性能为65.9dB，而原理图设计的后布局信噪比为67.8dB。
Existing analog layout synthesis tools provide little guarantee to post layout performance and have limited capabilities of handling system-level designs. In this paper, we present a closed-loop hierarchical analog layout synthesizer, capable of handling system designs. To ensure system performance, the building block layout implementations are optimized efficiently, utilizing post layout simulations with multi-objective Bayesian optimization. To the best of our knowledge, this is the first work demonstrating success in automated layout synthesis on generic analog system designs. Experimental results show our synthesized continuous-time ∆Σ modulator (CTDSM) achieves post layout performance of 65.9dB in signal to noise and distortion ratio (SNDR), compared with 67.8dB in the schematic design.