Future CMOS scaling and reliability
Future CMOS scaling and reliability
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未来 CMOS 缩放比例和可靠性
DOI：
10.1109/5.220900
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发表时间：
1993
期刊：
影响因子：
--
通讯作者：
C. Hu
中科院分区：
文献类型：
--
作者：
C. Hu
回顾了 MOSFET 缩放的目标和约束，并强调了可靠性约束的作用。结论是，MOSFET 器件尺寸的司法缩小可以通过 0.09μm (4-Gb SRAM) 技术来维持微缩的历史趋势，该技术可能会在 2010 年用于 IC 生产。电源电压的降低加上对大晶体管电流的需求将产生对能够承受更高电场的更薄栅极氧化物的需求。对于未来的复杂电路，内置可靠性必须取代传统的下线可靠性测试。电路可靠性仿真可能是实现内置可靠性的必要工具之一。 >
The goals and constraints of MOSFET scaling are reviewed, and the role of reliability constraints is highlighted. It is concluded that judicial shrinking of MOSFET device dimensions can sustain the historical trend of scaling through the 0.09- mu m (4-Gb SRAM) generation of technology, which may be used for IC production in the year 2010. Power supply voltage reduction plus the desire for large transistor current will create a demand for ever thinner gate oxides that can withstand ever higher electric field. Built-in reliability must replace the traditional end-of-the-line reliability testing for future complex circuits. Circuit reliability simulation may be one of the necessary tools for achieving built-in reliability. >