Defect-tolerant FPGA switch block and connection block with fine-grain redundancy for yield enhancement
Defect-tolerant FPGA switch block and connection block with fine-grain redundancy for yield enhancement
复制标题
具有细粒度冗余的容错 FPGA 开关模块和连接模块，可提高良率
DOI：
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发表时间：
2005
期刊：
影响因子：
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通讯作者：
G. Lemieux
中科院分区：
文献类型：
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作者：
A. Yu;G. Lemieux
未来的工艺节点具有如此小的特征尺寸，以至于每个管芯的制造缺陷数量将增加。对于大型FPGA，容忍多个缺陷将是至关重要的（Campregher等人，2005年）。我们提出了一些变化，详细的岛式FPGA的布线架构，以容忍多个随机的，分布式的互连缺陷，而无需重新布线，并对信号时序的影响最小。我们的方案是一个用户选项预建到一个架构，需要+11%的面积为额外的多路复用器。还需要未使用的（备用）布线轨道，使总开销达到24%，以容忍固定或开路故障，或34%，包括桥接。用户电路没有充分强调路由网络已经有这些轨道免费提供。延迟惩罚是可编程的：如果预期缺陷率足够低，则延迟惩罚为5-10%，但如果缺陷率很高，则延迟惩罚可以高达25%。我们的计划可以容忍超过10个互连缺陷的大阵列尺寸为128 /SPL倍/ 128。与行/列冗余方案不同，我们的方案是可扩展的：随着FPGA阵列大小的增加，它们自然会容忍更多的缺陷。这项工作是第一次详细分析的细粒度的缺陷容限方案在FPGA。
Future process nodes have such small feature sizes that there will be an increase in the number of manufacturing defects per die. For large FPGAs, it will be critical to tolerate multiple defects (Campregher et al., 2005). We propose a number of changes to the detailed routing architecture of island-style FPGAs to tolerate multiple random, distributed interconnect defects without re-routing and with minimal impact on signal timing. Our scheme is a user option prebuilt into an architecture, requiring +11% area for additional multiplexers. Unused (spare) wiring tracks are also needed, bringing total overhead to 24% to tolerate stuck-at or open faults, or 34% to include bridging. User circuits that do not fully stress the routing network already have these tracks freely available. The delay penalty is programmable: 5-10% if defect rates are expected to be sufficiently low, but can be as high as 25% if defect rates are high. Our schemes can tolerate more than 10 interconnect defects for large array sizes of 128 /spl times/ 128. Unlike row/column redundancy schemes, our schemes are scalable: they naturally tolerate more defects as the FPGA array size increases. This work is the first detailed analysis of fine-grained defect-tolerant schemes in FPGAs.