1600V 4H-SiC UMOSFETs with dual buffer layers
1600V 4H-SiC UMOSFETs with dual buffer layers
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DOI：
10.1109/ispsd.2005.1487988
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发表时间：
2005-05
期刊：
影响因子：
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通讯作者：
Q. Zhang;M. Gomez;C. Bui;E. Hanna
中科院分区：
文献类型：
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作者：
Q. Zhang;M. Gomez;C. Bui;E. Hanna
设计并制作了1600 V 4 H-SiCUMOSFETs，该器件采用了一种新型的双缓冲层结构，使沟槽刻蚀时间缩短了2/s/s/s/s，沟道周边密度达到3330 cm/cm/sup 2/s，同时具有较低的导通电阻。该器件的比导通电阻为50 m/spl Ω/-cm/sup 2/，沟道长度为1/spl μ/m，沟道长度小于1/spl μ/m，通过优化工艺可以进一步减小器件的比导通电阻。
This paper presents the design and fabrication of 1600V 4H-SiC UMOSFETs with a novel dual buffer layer structure, which shortens the trench etching time by 2/spl times/ and achieves a high channel periphery density of 3330cm/cm/sup 2/ for low specific on-resistance. The device exhibits 50m/spl Omega/-cm/sup 2/ of specific on-resistance with /spl sim/1/spl mu/m of channel length, and could be further reduced with <1/spl mu/m channel length and optimal fabrication process.