"Depletion isolation effect" of surrounding gate transistors
"Depletion isolation effect" of surrounding gate transistors
复制标题
周围栅极晶体管的“耗尽隔离效应”
DOI：
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发表时间：
1997
期刊：
影响因子：
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通讯作者：
F. Horiguchi
中科院分区：
文献类型：
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作者：
M. Terauchi;N. Shigyo;A. Nitayama;F. Horiguchi
制备了亚半微米环绕栅极晶体管（sgt），并研究了其电流-电压特性。即使在硅柱未完全耗尽的SGT中（例如，0.6 /spl mu/m SGT），通过使用硅柱的较低扩散层作为漏极并施加足够高的电压，完全耗尽器件固有的I-V特性（即低至60 mV/dec的亚阈值摆幅）。（与衬底偏置电压无关的阈值电压降低）观察到（“耗尽隔离效应”）。
Sub-half-micron surrounding gate transistors (SGTs) were fabricated and their current-voltage (I-V) characteristics were investigated. Even in a SGT whose Si pillar is not fully depleted (e.g., 0.6 /spl mu/m SGT), by using the lower diffusion layer of the Si pillar as drain and applying sufficiently high voltage, I-V characteristics inherent to fully depleted devices (i.e. subthreshold swing as low as 60 mV/dec., lowered threshold voltage independent of substrate bias voltage) were observed ("depletion isolation effect").