GPU-accelerated small delay fault simulation
GPU-accelerated small delay fault simulation
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DOI：
10.7873/date.2015.0077
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发表时间：
2015-03
期刊：
影响因子：
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通讯作者：
E. Schneider;S. Holst;M. Kochte;X. Wen;H. Wunderlich
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文献类型：
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作者：
E. Schneider;S. Holst;M. Kochte;X. Wen;H. Wunderlich
延迟故障的仿真是电路设计验证和可靠性评估中的一项重要工作。由于目前的纳米级设计对最小延迟偏差的高灵敏度，小延迟故障最近成为测试研究的焦点。由于延迟影响的细微性，传统的基于抽象时序模型的故障仿真方法不足以表示小延迟故障。因此，必须利用时序精确的仿真方法，由于高计算要求，这些方法很快变得不适用于较大的设计。在这项工作中，我们提出了一种波形准确的方法，快速高吞吐量的小延迟故障模拟图形处理单元（GPU）。通过利用门，故障和模式的并行性，所提出的方法使精确详尽的小延迟故障模拟，即使是数百万门的设计没有故障下降的第一次。
The simulation of delay faults is an essential task in design validation and reliability assessment of circuits. Due to the high sensitivity of current nano-scale designs against smallest delay deviations, small delay faults recently became the focus of test research. Because of the subtle delay impact, traditional fault simulation approaches based on abstract timing models are not sufficient for representing small delay faults. Hence, timing accurate simulation approaches have to be utilized, which quickly become inapplicable for larger designs due to high computational requirements. In this work we present a waveform-accurate approach for fast high-throughput small delay fault simulation on Graphics Processing Units (GPUs). By exploiting parallelism from gates, faults and patterns, the proposed approach enables accurate exhaustive small delay fault simulation even for multimillion gate designs without fault dropping for the first time.