Using pattern enumeration to accelerate process development and ramp yield
Using pattern enumeration to accelerate process development and ramp yield
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使用模式枚举加速工艺开发并提高产量
DOI：
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发表时间：
2016
期刊：
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通讯作者：
Hua Ding
中科院分区：
文献类型：
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作者：
Linda Zhuang;Jenny Pang;Jessy Xu;Mengfeng Tsai;Amy Wang;Yifan Zhang;Jason Sweis;Ya;Hua Ding
在新技术节点工艺设置阶段，代工厂最初没有足够的产品芯片设计来进行详尽的工艺开发。不同的操作团队使用手工设计的简单测试键来设置他们的流程流和配方。当设计规则手册（DRM）的第一个版本准备好时，代工厂进入工艺开发阶段，在此阶段，新的实验设计数据是基于这些设计规则手动创建的。然而，这些IP/测试键包含非常统一或简单的设计结构。这种设计通常不包含关键的设计结构或过程不友好的设计模式，这些设计模式通过了设计规则检查，但被发现不易制造。在开发阶段，需要有一种方法来生成设计规则所允许的详尽测试模式，以验证设计规则与过程之间的差距。本文提出了一种生成测试键模式的新方法，该方法既包含已知的问题模式，也包含设计者根据现有设计规则可能绘制的任何结构。列举的测试键模式将包含任何特定设计规则所允许的最关键的设计结构。为了发现新产品的潜在弱点，晶圆厂可以采取先发制人的措施来避免良率损失，采用布局分析方法对设计芯片进行分析。它可以通过比较不同的产品，并利用从以前制造的芯片中学到的知识来找到可能的产量贬低者来实现。
During a new technology node process setup phase, foundries do not initially have enough product chip designs to conduct exhaustive process development. Different operational teams use manually designed simple test keys to set up their process flows and recipes. When the very first version of the design rule manual (DRM) is ready, foundries enter the process development phase where new experiment design data is manually created based on these design rules. However, these IP/test keys contain very uniform or simple design structures. This kind of design normally does not contain critical design structures or process unfriendly design patterns that pass design rule checks but are found to be less manufacturable. It is desired to have a method to generate exhaustive test patterns allowed by design rules at development stage to verify the gap of design rule and process. This paper presents a novel method of how to generate test key patterns which contain known problematic patterns as well as any constructs which designers could possibly draw based on current design rules. The enumerated test key patterns will contain the most critical design structures which are allowed by any particular design rule. A layout profiling method is used to do design chip analysis in order to find potential weak points on new incoming products so fab can take preemptive action to avoid yield loss. It can be achieved by comparing different products and leveraging the knowledge learned from previous manufactured chips to find possible yield detractors.