Fin-Height Effect on Poly-Si/PVD-TiN Stacked-Gate FinFET Performance
Fin-Height Effect on Poly-Si/PVD-TiN Stacked-Gate FinFET Performance
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鳍片高度对多晶硅/PVD-TiN 堆叠栅极 FinFET 性能的影响
DOI：
10.1109/ted.2011.2181385
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发表时间：
2012
期刊：
影响因子：
--
通讯作者：
et al
中科院分区：
文献类型：
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作者：
Tetsuro Hayashida;et al
比较了不同鳍高Hfin的n+-poly-Si/PVD-TiN叠栅FinFET的电学特性，包括迁移率和通态电流Ion。在具有较高鳍的器件中，由于增加的张应力，迁移率增强。然而，随着栅极长度Lg减小，具有高鳍的Ionfor器件变得更差，可能是由于高寄生电阻Rp。此外，由于鳍片侧壁的粗糙蚀刻，Vth变化随着Hfin的增加而增加。降低Rp的工艺技术和产生光滑精确轮廓的蚀刻技术对于开发高性能FinFET至关重要。
We compared the electrical characteristics, including mobility and on -state currentIon, of n+-poly-Si/PVD-TiN stacked-gate FinFETs with different fin heightsHfin. The mobility was enhanced in devices with taller fins due to increased tensile stress. However, as gate lengthLgdecreases,Ionfor devices with tall fins becomes worse, probably due to a high parasitic resistanceRp. Furthermore,Vthvariation increased with increasingHfindue to rough etching of the fin sidewall. Process technologies for reducingRpand etching technology that yields smooth precise profiles are essential to exploit the high performance of tall FinFETs.