NBTI-aware design of NoC buffers
NBTI-aware design of NoC buffers
复制标题
NoC 缓冲区的 NBTI 感知设计
DOI：
10.1145/2482759.2482766
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发表时间：
2013
期刊：
影响因子：
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通讯作者：
W. Fornaciari
中科院分区：
文献类型：
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作者：
Davide Zoni;W. Fornaciari
片上网络 (NoC) 在确定当前和未来多核架构的性能和可靠性方面发挥着核心作用。 CMOS 技术的不断扩展使得多核架构得以广泛采用，但不幸的是，这也引发了对故障的严重担忧。工艺偏差 (PV) 使情况变得更糟，降低了芯片制造过程中的器件寿命和性能可预测性。本文提出了两种利用功率门控来应对 NoC 缓冲区中 NBTI 效应的解决方案。在存在过程变化的情况下，针对可变数量的虚拟通道 (VC) 来评估这些技术。此外，还考虑了功率门控延迟开销。实验表明，与基准 NoC 相比，净 NBTI Vth 节省高达 54.2%，面积开销低于 5%。
Network-on-Chips (NoC) play a central role in determining performance and reliability in current and future multi-core architectures. Continuous scaling of CMOS technology enable widespread adoption of multi-core architectures but, unfortunately, poses severe concerns regarding failures. Process variation (PV) is worsening the scenario, decreasing device lifetime and performance predictability during chip fabrication. This paper proposes two solutions exploiting power-gating to cope with NBTI effects in NoC buffers. The techniques are evaluated with respect to a variable number of virtual channels (VCs), in the presence of process variation. Moreover, power gating delay overhead is accounted. Experiments reveal a net NBTI Vth saving up to 54.2% against the baseline NoC, with an area overhead below 5%.