CMOS scaling into the nanometer regime
CMOS scaling into the nanometer regime
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DOI：
10.1109/5.573737
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发表时间：
1997-04-01
影响因子：
20.6
通讯作者：
Wong, HS
中科院分区：
文献类型：
--
作者：
Taur, Y;Buchanan, DA;Wong, HS
本文首先简要回顾了0.1微米(100 Nm)CMOS的发展现状，然后从基本物理效应和实际考虑出发，讨论了将CMOS技术进一步扩展到纳米(100 nm以下)的关键挑战。讨论的问题包括：光刻、电源和阈值电压、短沟道效应、栅氧化物、高场效应、掺杂数量波动和互连延迟。文章的最后部分讨论了几种替代或非传统的器件结构，包括绝缘体上硅(SOI)、SiGe MOSFET、低温CMOS和双栅MOSFET，它们可能会把我们带到硅尺寸的最外极限。
Starting with a brief review on 0.1-mu m (100 nm) CMOS status, this paper addresses the key challenges in further scaling of CMOS technology into the nanometer (sub-100 nm) regime in light of fundamental physical effects and practical considerations. Among the issues discussed are: lithography, power supply and threshold voltage, short-channel effect, gate oxide, high-field effects, dopant number fluctuations, and interconnect delays. The last part of the paper discusses several alternative or unconventional device structures, including silicon-on-insulator (SOI), SiGe MOSFET's, low-temperature CMOS, and double-gate MOSFET's, which may take us to the outermost limits of silicon scaling.