A Dual-Split-Controlled 4P2N 6T SRAM in Monolithic 3D-ICs With Enhanced Read Speed and Cell Stability for IoT Applications
A Dual-Split-Controlled 4P2N 6T SRAM in Monolithic 3D-ICs With Enhanced Read Speed and Cell Stability for IoT Applications
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DOI：
10.1109/led.2018.2850322
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发表时间：
2018-06
影响因子：
4.9
通讯作者：
Wei-Hao Chen;Chien-Fu Chen;Yi-Ju Chen;Hsiao-Yun Chiu;C. Shen;J. Shieh;F. Hsueh;Chih-Chao Yang;Bo-Yuan Chen;G. Huang;Kai-Shin Li;W. Yeh;H. Yamauchi;Meng-Fan Chang
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文献类型：
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作者：
Wei-Hao Chen;Chien-Fu Chen;Yi-Ju Chen;Hsiao-Yun Chiu;C. Shen;J. Shieh;F. Hsueh;Chih-Chao Yang;Bo-Yuan Chen;G. Huang;Kai-Shin Li;W. Yeh;H. Yamauchi;Meng-Fan Chang
与使用现有工艺获得的驱动能力相比，最近的单片3-D集成电路（3D-IC）技术倾向于在pMOS晶体管中诱导更强的驱动能力。因此，传统的6 T SRAM在用于单片3D-IC中时遭受访问速度和写入裕度的劣化。这封信提出了一个双分裂控制的4P 2N（DSC-4P 2N）SRAM与相应的读取和写入辅助方案，能够提供更大的单元读取电流和更高的写裕度相比，在单片3D-IC中实现的4 N2 P SRAM。与不带DSC的4P 2N SRAM相比，所提出的DSC方案在读取稳定性方面提高了4.8倍。在单片3D-IC中制作的DSC-4P 2N SRAM性能优于以前的6 T SRAM。
Recent monolithic 3-D integrated-circuit (3D-IC) technology tends to induce stronger driving capability in pMOS transistors, compared to that obtained using existing processes. Thus, conventional 6T SRAMs suffer degradation in access speed and write margin when used in monolithic 3D-ICs. This letter proposes a dual-split-controlled 4P2N (DSC-4P2N) SRAM with corresponding read and write assist schemes capable of providing a larger cell read current and higher write margins compared to 4N2P SRAMs implemented in monolithic 3D-ICs. The proposed DSC scheme improves $4.8\times $ in read stability compared to 4P2N SRAM without DSC. A fabricated DSC-4P2N SRAM in monolithic 3D-IC was shown to outperform the previous 6T SRAMs.