Approximate logic synthesis for error tolerant applications
Approximate logic synthesis for error tolerant applications
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DOI：
10.1109/date.2010.5456913
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发表时间：
2010-03
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通讯作者：
Doochul Shin;S. Gupta
中科院分区：
文献类型：
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作者：
Doochul Shin;S. Gupta
容错性正式地捕获了以下概念：对于包括音频、视频、图形和无线通信在内的各种应用，在其输出端产生错误值的有缺陷的芯片可以是可接受的，只要错误是某些类型的并且其严重性在应用指定的阈值内。所有以前的容错研究都集中在制造后测试期间识别这种有缺陷但可接受的芯片，以提高成品率。在本文中，我们探索了一种全新的方法，利用误差容限的基础上观察：如果某些偏离标称输出值是可以接受的，那么我们可以利用这种灵活性在电路设计，以减少电路面积和延迟，以及提高产量。我们关注的容错性的具体度量是错误率，即，电路产生错误输出的频率。我们提出了一种新的逻辑综合方法的新问题，确定如何利用一个给定的错误率阈值，以最大限度地减少合成电路的面积。实验结果表明，对于1%以内的错误率阈值，我们的方法提供了9.43%的文字减少平均为所有的基准，我们的目标。
Error tolerance formally captures the notion that - for a wide variety of applications including audio, video, graphics, and wireless communications - a defective chip that produces erroneous values at its outputs may be acceptable, provided the errors are of certain types and their severities are within application-specified thresholds. All previous research on error tolerance has focused on identifying such defective but acceptable chips during post-fabrication testing to improve yield. In this paper, we explore a completely new approach to exploit error tolerance based on the following observation: If certain deviations from the nominal output values are acceptable, then we can exploit this flexibility during circuit design to reduce circuit area and delay as well as to increase yield. The specific metric of error tolerance we focus on is error rate, i.e., how often the circuit produces erroneous outputs. We propose a new logic synthesis approach for the new problem of identifying how to exploit a given error rate threshold to maximally reduce the area of the synthesized circuit. Experiment results show that for an error rate threshold within 1%, our approach provides 9.43% literal reductions on average for all the benchmarks that we target.