Vertical Gate-All-Around Nanowire GaSb-InAs Core-Shell n-Type Tunnel FETs
Vertical Gate-All-Around Nanowire GaSb-InAs Core-Shell n-Type Tunnel FETs
复制标题
垂直栅极全方位纳米线 GaSb-InAs 核壳 n 型隧道 FET
作者：
T. Vasen;P. Ramvall;A. Afzalian;G. Doornbos;M. Holland;C. Thelander;K. Dick;L. Wernersson;M. Passlack
隧道效应晶体管(TFET)是未来包括移动和物联网(IoT)产品在内的低功耗CMOS应用的最有前途的候选者之一。采用核壳(C-S)结构的垂直栅极全能(VGaA)架构是满足CMOS版图要求的领先竞争者，同时提供高性能规格的高电流驱动和低功耗操作的亚阈值摆幅低于博尔兹曼限制。在这项工作中，首次实验证明了VGaA纳米线GaSb/InAs C-S TFET的关键器件性能为：亚阈值摆幅S = 40 mV/dec(Vd = 10 mV)，电流驱动高达40μA/线(Vd = 0.3 V，直径d = 50 nm)，同时核心直径d、壳层厚度和栅长等尺寸也达到了要求。结合TCAD建模的实验数据揭示了界面陷阱密度的要求，以达到行业标准的非电流规范。
Tunneling Field-Effect Transistors (TFET) are one of the most promising candidates for future low-power CMOS applications including mobile and Internet of Things (IoT) products. A vertical gate-all-around (VGAA) architecture with a core shell (C-S) structure is the leading contender to meet CMOS footprint requirements while simultaneously delivering high current drive for high performance specifications and subthreshold swing below the Boltzmann limit for low power operation. In this work, VGAA nanowire GaSb/InAs C-S TFETs are demonstrated experimentally for the first time with key device properties of subthreshold swing S = 40 mV/dec (Vd = 10 mV) and current drive up to 40 μA/wire (Vd = 0.3 V, diameter d = 50 nm) while dimensions including core diameter d, shell thickness and gate length are scaled towards CMOS requirements. The experimental data in conjunction with TCAD modeling reveal interface trap density requirements to reach industry standard off-current specifications.