High-performance field programmable VLSI processor based on a direct allocation of a control/data flow graph
High-performance field programmable VLSI processor based on a direct allocation of a control/data flow graph
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基于控制/数据流图直接分配的高性能现场可编程 VLSI 处理器
DOI：
10.1109/isvlsi.2002.1016881
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发表时间：
2002
期刊：
影响因子：
--
通讯作者：
M. Kameyama
中科院分区：
文献类型：
--
作者：
Naotaka Ohsawa;M. Hariyama;M. Kameyama
本文提出了一种高性能现场可编程VLSI处理器（FPVLSI），其中引入位串行处理元件（PE）阵列来降低可编程互连网络的复杂性。因此，可以大大减少互连网络中交换块的面积和延迟。此外，采用控制/数据流图的直接分配，仅将单个节点映射到PE，从而大大降低了布线复杂度。具有 4400 个 PE 的 FPVLSI 采用 0.35 /spl mu/m CMOS 工艺设计。在执行 16 点 FFT 时，FPVLSI 的性能经评估比典型 FPGA 高 28 倍。
This paper proposes a high-performance field programmable VLSI processor (FPVLSI), in which a bit-serial processing element (PE) array is introduced to reduce the complexity of programmable interconnection networks. Therefore, the area and delay of a switch block in the interconnection network can be greatly reduced. Moreover, direct allocation of a control/data flow graph is employed where only a single node is mapped into a PE so that the wiring complexity is greatly reduced. The FPVLSI with 4400 PEs is designed in a 0.35 /spl mu/m CMOS process. The performance of the FPVLSI is evaluated to be 28 times higher than that of the typical FPGA when executing the 16-point FFT.