A Highly Robust, Low Delay and DNU-Recovery Latch Design for Nanoscale CMOS Technology
A Highly Robust, Low Delay and DNU-Recovery Latch Design for Nanoscale CMOS Technology
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DOI：
10.1145/3526241.3530321
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发表时间：
2022-06
期刊：
影响因子：
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通讯作者：
Aibin Yan;Zhen Zhou;Shaojie Wei;Jie Cui;Yong Zhou;Tianming Ni;P. Girard;X. Wen
中科院分区：
文献类型：
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作者：
Aibin Yan;Zhen Zhou;Shaojie Wei;Jie Cui;Yong Zhou;Tianming Ni;P. Girard;X. Wen
随着半导体技术的发展，纳米级CMOS电路已经变得更容易受到软误差的影响，例如单个节点 - UPSETS（SNUS）和Double-Node-Upsets（DNUS）。为了有效耐受辐射引起的DNU并减少闩锁的延迟和面积消耗，本文提出了纳米级CMOS技术中的DNU弹性闩锁。闩锁主要包括四个输入分解逆变器和四个2输入C元素。由于所有内部节点都是互锁的，因此闩锁可以从所有可能的DNU中恢复。仿真结果表明，与最先进的DNU自我恢复闩锁设计相比，所提出的闩锁可以平均节省64.51％的传输延迟和56.88％的延迟区域驱动器（DAPP）。
With the advancement of semiconductor technologies, nano-scale CMOS circuits have become more vulnerable to soft errors, such as single-node-upsets (SNUs) and double-node-upsets (DNUs). In order to effectively tolerate DNUs caused by radiation and reduce the delay and area consumption of latches, this paper proposes a DNU resilient latch in the nanoscale CMOS technology. The latch mainly comprises four input-split inverters and four 2-input C-elements. Since all internal nodes are interlocked, the latch can recover from all possible DNUs. Simulation results show that, compared with the state-of-the-art DNU self-recovery latch designs, the proposed latch can save 64.51% transmission delay and 56.88% delay-area-power-product (DAPP) on average, respectively.