Skywalk: A Topology for HPC Networks with Low-Delay Switches
Skywalk: A Topology for HPC Networks with Low-Delay Switches
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DOI：
10.1109/ipdps.2014.37
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发表时间：
2014-05
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影响因子：
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通讯作者：
I. Fujiwara;M. Koibuchi;Hiroki Matsutani;H. Casanova
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文献类型：
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作者：
I. Fujiwara;M. Koibuchi;Hiroki Matsutani;H. Casanova
随着低延迟交换机的出现，大规模高性能计算（HPC）互连中的端到端延迟将由电缆延迟主导。在这种情况下，我们定义了一个新的网络拓扑结构，Skywalk，部署低延迟互连在即将到来的HPC系统。Skywalk使用随机性来实现低延迟，但这样做的方式是考虑到拓扑的物理布局，从而导致进一步的电缆长度，从而减少延迟。通过图形分析和离散事件模拟，我们表明，Skywalk比较有利（在延迟，电缆长度和吞吐量方面），传统的低度环面和中度超立方体拓扑结构，高度全连接的蜻蜓拓扑结构，HyperX拓扑结构，最近提出的完全随机拓扑结构。
With low-delay switches on the horizon, end-to-end latency in large-scale High Performance Computing (HPC) interconnects will be dominated by cable delays. In this context we define a new network topology, Skywalk, for deploying low-latency interconnects in upcoming HPC systems. Skywalk uses randomness to achieve low latency, but does so in a way that accounts for the physical layout of the topology so as to lead to further cable length and thus latency reductions. Via graph analysis and discrete-event simulation we show that Skywalk compares favorably (in terms of latency, cable length, and throughput) to traditional low-degree torus and moderate-degree hypercube topologies, to high-degree fully-connected Dragonfly topologies, to the HyperX topology, and to recently proposed fully random topologies.