Characteristics and device design of sub-100 nm strained Si N- and PMOSFETs-猫眼课题宝

DOI：

10.1109/vlsit.2002.1015406

发表时间：

2002-06

期刊：

2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303)

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其他

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作者：

Kern Rim;J. O. Chu;Huajie Chen;Keith A. Jenkins;T. Kanarsky;Kam-Leung Lee;Anda C. Mocuta;Huilong Zhu;R. Roy;J. Newbury;John A. Ott;K. Petrarca;Patricia M. Mooney;D. Lacey;S. J. Koester;K. K. Chan-K.;Diane C. Boyd;M. Ieong;Hon-Sum Philip Wong

首次在具有亚100 nm物理栅极长度的应变Si PMOSFET中证明了电流驱动增强，以及在具有良好控制的阈值电压V/sub T/和重叠电容C/sub OV/特性的NMOSFET中，L/sub poly/和L/sub eff/低于80 nm和60 nm。在具有1.2%拉伸应变（在弛豫SiGe缓冲层中28%Ge含量）的应变Si器件中观察到电子迁移率的110%的增强，沿着峰值空穴迁移率增加45%。

Current drive enhancements were demonstrated in the strained-Si PMOSFETs with sub-100 nm physical gate lengths for the first time, as well as in the NMOSFETs with well-controlled threshold voltage V/sub T/ and overlap capacitance C/sub OV/ characteristics for L/sub poly/ and L/sub eff/ below 80 nm and 60 nm. A 110% enhancement in the electron mobility was observed in the strained Si devices with 1.2% tensile strain (28% Ge content in the relaxed SiGe buffer), along with a 45% increase in the peak hole mobility.

Characteristics and device design of sub-100 nm strained Si N- and PMOSFETs

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