The Impact of BTI Variations on Timing in Digital Logic Circuits
The Impact of BTI Variations on Timing in Digital Logic Circuits
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DOI：
10.1109/tdmr.2013.2237910
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发表时间：
2013-01
影响因子：
2
通讯作者：
Jian-wei Fang;S. Sapatnekar
中科院分区：
文献类型：
--
作者：
Jian-wei Fang;S. Sapatnekar
提出了一种分析大规模数字逻辑电路中偏置温度不稳定性（BTI）变化对时序影响的新框架。这种方法结合了反应扩散模型和电荷捕获模型的BTI和嵌入到一个时间统计静态时序分析框架捕捉过程的变化和路径的相关性。32-，22-，和16-nm的技术模型，这是通过蒙特卡罗模拟验证的实验结果，证实了所提出的方法是快速，准确，可扩展的，并表明BTI的变化作出重大贡献的电路级时序变化。
A new framework for analyzing the impact of bias temperature instability (BTI) variations on timing in large-scale digital logic circuits is proposed in this paper. This approach incorporates both the reaction-diffusion model and the charge-trapping model for BTI and embeds these into a temporal statistical static timing analysis framework capturing process variations and path correlations. Experimental results on 32-, 22-, and 16-nm technology models, which were verified through Monte Carlo simulation, confirm that the proposed approach is fast, accurate, and scalable and indicate that BTI variations make a significant contribution to circuit-level timing variations.