Top-Gated Silicon Nanowire Transistors in a Single Fabrication Step
Top-Gated Silicon Nanowire Transistors in a Single Fabrication Step
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DOI：
10.1021/nn900284b
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发表时间：
2009-06-01
期刊：
影响因子：
17.1
通讯作者：
Ferrari, Andrea C.
中科院分区：
文献类型：
--
作者：
Colli, Alan;Tahraoui, Abbes;Ferrari, Andrea C.
顶栅硅纳米线晶体管是通过剂量调制电子束光刻在单个步骤中在纳米线顶部制备所有端子（源极、漏极和栅极）来制造的。这优于其他需要对准多个图案的耗时方法，其中对准公差对器件缩放施加限制。我们使用10-15 nm的SiO2壳作为栅极电介质，该壳在硅纳米线的气相传输生长过程中自然形成，因此该线可以在合成后实施到器件中，而无需额外的处理。这种天然氧化物外壳在工作范围内的泄漏可以忽略不计。我们的单步图案化是实现短沟道纳米线晶体管的最实用的路线，可以应用于一些纳米器件的几何形状，需要非等效电极。
Top-gated silicon nanowire transistors are fabricated by preparing all terminals (source, drain, and gate) on top of the nanowire in a single step via dose-modulated e-beam lithography. This outperforms other time-consuming approaches requiring alignment of multiple patterns, where alignment tolerances impose a limit on device scaling. We use as gate dielectric the 10-15 nm SiO2 shell naturally formed during vapor-transport growth of Si nanowires, so the wires can be implemented into devices after synthesis without additional processing. This natural oxide shell has negligible leakage over the operating range. Our single-step patterning is a most practical route for realization of short-channel nanowire transistors and can be applied to a number of nanodevice geometries requiring nonequivalent electrodes.