Evaluation of the statistical delay quality model
Evaluation of the statistical delay quality model
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DOI：
10.1145/1120725.1120856
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发表时间：
2005-01
期刊：
影响因子：
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通讯作者：
Yasuo Sato;S. Hamada;T. Maeda;Atsuo Takatori;S. Kajihara
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文献类型：
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作者：
Yasuo Sato;S. Hamada;T. Maeda;Atsuo Takatori;S. Kajihara
在本文中，我们介绍了一个质量模型，反映了制造工艺质量，设计延迟裕度和测试时序精度。该模型提供了一种测量方法，可以预测导致延迟故障的芯片缺陷的水平，包括边际延迟。因此，我们可以使用该模型，使测试向量是有效的测试成本和芯片质量。使用ISCAS89基准数据和一些大型工业设计数据的实验结果反映了我们的统计延迟质量模型的各种特性。
In this paper we introduce a quality model that reflects fabrication process quality, design delay margin, and test timing accuracy. The model provides a measure that can predict the level of chip defects that cause delay failure, including marginal delay. We can therefore use the model to make test vectors that are effective in terms of both testing cost and chip quality. The results of experiments using ISCAS89 benchmark data and some large industrial design data reflect various characteristics of our statistical delay quality model.