Algorithms and VLSI Architectures for Low-Density Parity-Check Codes: Part 1-Low-Complexity Iterative Decoding

Algorithms and VLSI Architectures for Low-Density Parity-Check Codes: Part 1-Low-Complexity Iterative Decoding
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低密度奇偶校验码的算法和 VLSI 架构:第 1 部分 - 低复杂度迭代解码

DOI:
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发表时间:
2016
期刊:
IEEE Solid-State Circuits Magazine
影响因子:
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通讯作者:
F. García
F. García
中科院分区:
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文献类型:
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作者:
K. Gunnam;Joan Marc Catala Perez;F. García

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本文是有关低密度奇偶校验 (LDPC) 码的两部分教程的第一篇。这些代码已被牢固地确立为通信和存储通道的纠错编码技术。
This article is the first of a two-part tutorial about low-density parity-check (LDPC) codes. These codes have been firmly established as error-correction coding techniques for communication and storage channels.