Erasure error correction with hardware detection
Erasure error correction with hardware detection
复制标题
通过硬件检测进行擦除错误纠正
DOI：
10.1109/dftvs.1999.802896
复制
发表时间：
1999
期刊：
影响因子：
--
通讯作者：
Jien
中科院分区：
文献类型：
--
作者：
W. Armitage;Jien
错误控制编码方法一直是保护数字通信不受传输错误影响的主要方法。这些代码被很好地理解，它们的错误检测和纠正能力在文献中得到了明确的确立。为了纠正错误，需要错误位置；因此，错误控制码的检测能力大大超过了纠错能力。如果可以在处理之前通过代码检查电路确定并提供错误位置信息，则在特殊情况下可以显著增强这种纠正能力。其中一种情况是比特“擦除”。这项工作的重点是使用未定义的逻辑电平（既不在V/sub dd/附近，也不在V/sub ss/附近）作为擦除检测方法。展示了如何通过预检测擦除来增强各种d/sub / min/纠错码的纠错能力。给出了一个实现实例：描述了这种基于9位奇偶校验的擦除校正电路；本文给出了该电路的测试结果，并与一个简单的奇偶校验器的性能进行了比较。给出了向高阶码扩展的具体细节。
Error-control coding methods have been the primary method used to protect digital communications from transmission errors. Such codes are well understood and their capabilities for error detection and correction clearly established in the literature. For correction purposes, error location is required; for this reason error-control codes' detection capabilities significantly exceed their correction capabilities. If error location information can be determined and supplied prior to processing by code-checking circuitry, such correction capability can be significantly enhanced in special circumstances. One such circumstance is that of bit "erasures". This work focuses on the use of undefined logic levels (near neither V/sub dd/ nor V/sub ss/) as an erasure detection method. It is shown how the error correction capabilities of error-correction codes of various d/sub min/ are enhanced by pre-detection of erasures. An implementation example is presented: this 9-bit parity-based erasure correction circuit is described; test results of the the fabricated circuit are presented as a comparison with capabilities of a simple parity checker. Specific details of extension to higher-order codes are presented.