A 1.8-V 12-bit 250-MS/s 25-mW self-calibrated DAC
A 1.8-V 12-bit 250-MS/s 25-mW self-calibrated DAC
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DOI：
10.1109/esscirc.2010.5619889
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发表时间：
2010-11
期刊：
影响因子：
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通讯作者：
Jen-Hung Chi;Shih-Hsuan Chu;T. Tsai
中科院分区：
文献类型：
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作者：
Jen-Hung Chi;Shih-Hsuan Chu;T. Tsai
介绍了一种12位电流舵自校准数模转换器（DAC）。通过校准方案补偿了电流源之间的失配，从而在保证DAC线性度的同时减小了有源面积。该数模转换器采用0.18μ mCMOS工艺实现，有源区面积小于0.8mm2。经校准后，测量的微分和积分非线性均在±0.5 LSB以内。在250 MSample/s时，当输入信号为1 MHz时，SFDR优于71.68 dB。该DAC采用1.8 V电源供电时功耗为25 mW。
A 12-bit current-steering self-calibrated digital-to-analog converter (DAC) is presented. Mismatches among the current sources are compensated by the calibration scheme, so that the DAC linearity is ensured and the active area is small at the same time. This digital-to-analog data converter was implemented in a 0.18μm CMOS process, and the active area is smaller than 0.8 mm2. After calibration, the measured differential and integral nonlinearity are both within ±0.5 LSB. At 250-MSample/s, the SFDR is better than 71.68 dB when the input signal is 1-MHz. This DAC dissipates 25mW from a 1.8-V supply.