Finite Alphabet Iterative Decoders for LDPC Codes: Optimization, Architecture and Analysis
Finite Alphabet Iterative Decoders for LDPC Codes: Optimization, Architecture and Analysis
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DOI：
10.1109/tcsi.2014.2309896
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发表时间：
2014-03
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通讯作者：
Fang Cai;Xinmiao Zhang;D. Declercq;S. Planjery;B. Vasic
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作者：
Fang Cai;Xinmiao Zhang;D. Declercq;S. Planjery;B. Vasic
低密度奇偶校验（LDPC）码由于其逼近香农限的纠错性能而被广泛应用。然而，这些码的基于置信传播（BP）的解码遭受错误平层问题，即，错误率曲线的斜率在非常低的错误率时发生突变。最近，一种新类型的解码器称为有限字母迭代解码器（FAID）的介绍。FAID使用简单的布尔映射进行可变节点处理，并且可以在具有非常短的字长的错误平层区域中超过基于BP的解码器。我们将本文的范围限制在BSC信道上的常规dv=3 LDPC码。本文提出了一种低复杂度的实现架构的FAID，利用他们的属性。特别是，一个创新的比特串行校验节点单元设计的FAID，并提出了一个小面积的可变节点单元，利用布尔映射的对称性。此外，提出了一种优化的数据调度方案，以提高硬件利用率。从综合结果来看，所提出的FAID实现仅需要52%的面积来达到与用于示例（7807，7177）LDPC码的最高效的标准最小和解码器之一相同的吞吐量，同时在错误平层区域中实现更好的纠错性能。与具有较长字长的偏移最小和解码器相比，所提出的设计可以以45%的面积实现更高的吞吐量，并且仍然导致在错误平层区域中可能的性能改善。
Low-density parity-check (LDPC) codes are adopted in many applications due to their Shannon-limit approaching error-correcting performance. Nevertheless, belief-propagation (BP) based decoding of these codes suffers from the error-floor problem, i.e., an abrupt change in the slope of the error-rate curve that occurs at very low error rates. Recently, a new type of decoders termed finite alphabet iterative decoders (FAIDs) were introduced. The FAIDs use simple Boolean maps for variable node processing, and can surpass the BP-based decoders in the error floor region with very short word length. We restrict the scope of this paper to regular dv=3 LDPC codes on the BSC channel. This paper develops a low-complexity implementation architecture for the FAIDs by making use of their properties. Particularly, an innovative bit-serial check node unit is designed for the FAIDs, and a small-area variable node unit is proposed by exploiting the symmetry in the Boolean maps. Moreover, an optimized data scheduling scheme is proposed to increase the hardware utilization efficiency. From synthesis results, the proposed FAID implementation needs only 52% area to reach the same throughput as one of the most efficient standard Min-Sum decoders for an example (7807, 7177) LDPC code, while achieving better error-correcting performance in the error-floor region. Compared to an offset Min-Sum decoder with longer word length, the proposed design can achieve higher throughput with 45% area, and still leads to possible performance improvement in the error-floor region.