Tile size selection for optimized memory reuse in high-level synthesis
Tile size selection for optimized memory reuse in high-level synthesis
复制标题
在高级综合中优化内存重用的分块大小选择
DOI：
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发表时间：
2017
期刊：
影响因子：
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通讯作者：
G. Constantinides
中科院分区：
文献类型：
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作者：
Junyi Liu;John Wickerson;G. Constantinides
高级合成（HLS）能够为FPGA加速器生成控制和计算电路，但仍需要足够的人力来应对记忆和通信瓶颈的挑战。 - 循环瓷砖。显着影响记忆需求，通常是通过部分枚举来确定的。为了确定在受约束的芯片内存中的数据重复使用的瓷砖大小，然后开发出一种算法以优化该模型，使用非线性求解器将交流式求职者最小化。同一时间，我们提出的方法可以产生瓷砖大小，从而导致沟通开销的平均水平减少75％。
High-level synthesis (HLS) is well capable of generating control and computation circuits for FPGA accelerators, but still requires sufficient human effort to tackle the challenge of memory and communication bottlenecks. One important approach for improving data locality is to apply loop tiling on memory-intensive loops. Loop tiling is a well-known compiler technique that partitions the iteration space of a loop nest into chunks (or ‘tiles’) whose associated data can fit into size-constrained fast memory. The size of the tiles, which can significantly affect the memory requirement, is usually determined by partial enumeration. In this paper, we propose an analytical methodology to select a tile size for optimized memory reuse in HLS. A parametric polyhedral model is introduced to capture memory usage analytically for arbitrary tile sizes. To determine the tile size for data reuse in constrained on-chip memory, an algorithm is then developed to optimize over this model, using non-linear solvers to minimize communication overhead. Experimental results on three representative loops show that, compared to random enumeration with the same time budget, our proposed method can produce tile sizes that lead to a 75% average reduction in communication overhead. A case study with real hardware prototyping also demonstrates the benefits of using the proposed tile size selection.