Step Persistence in the Design of GALS Systems
Step Persistence in the Design of GALS Systems
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DOI：
10.1007/978-3-642-38697-8_11
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发表时间：
2013-06
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通讯作者：
Johnson Fernandes;M. Koutny;Marta Pietkiewicz-Koutny;D. Sokolov;A. Yakovlev
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文献类型：
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作者：
Johnson Fernandes;M. Koutny;Marta Pietkiewicz-Koutny;D. Sokolov;A. Yakovlev
在本文中，我们研究了GALS（全局异步局部同步）系统在VLSI电路中的行为。系统的规格以Petri网的形式给出。我们的目标是通过将并发事件分组在一起来重新设计系统以优化信号管理。查看给定Petri网的并发可达性图，我们感兴趣的是发现出现在“bundle”中的事件，以便它们都可以在一个时钟周期内执行。bundle的最佳候选对象是在相同配置中反复出现的事件集，形成“持久”的事件集。到目前为止，只在顺序语义上下文中考虑了持久性。这里我们引入了持久步骤的概念，并讨论了它们的基本性质。然后，我们引入了束的正式定义，并提出了一种算法来修剪系统的行为，以便只保留束步骤。修剪后的可达性图表示一个重新设计的系统的行为，这反过来又可以使用网络合成的标准技术在一个新的Petri网中实现。该算法对持久网络和安全网络的可达性图进行修剪，留下表示最大并发步骤的包。
In this paper we investigate the behaviour of GALS (Globally Asynchronous Locally Synchronous) systems in the context of VLSI circuits. The specification of a system is given in the form of a Petri net. Our aim is to re-design the system to optimise signal management, by grouping together concurrent events. Looking at the concurrent reachability graph of the given Petri net, we are interested in discovering events that appear in ‘bundles’, so that they all can be executed in one clock tick. The best candidates for bundles are sets of events that appear and re-appear over and over again in the same configurations, forming ‘persistent’ sets of events. Persistence was considered so far only in the context of sequential semantics. Here we introduce a notion of persistent steps and discuss their basic properties. We then introduce a formal definition of a bundle and propose an algorithm to prune the behaviour of a system, so that only bundle steps remain. The pruned reachability graph represents the behaviour of a re-engineered system, which in turn can be implemented in a new Petri net using the standard techniques of net synthesis. The proposed algorithm prunes reachability graphs of persistent and safe nets leaving bundles that represent maximally concurrent steps.