A fully integrated reprogrammable memristor-CMOS system for efficient multiply-accumulate operations
A fully integrated reprogrammable memristor-CMOS system for efficient multiply-accumulate operations
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DOI：
10.1038/s41928-019-0270-x
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发表时间：
2019-07-01
影响因子：
34.3
通讯作者：
Lu, Wei D.
中科院分区：
文献类型：
--
作者：
Cai, Fuxi;Correll, Justin M.;Lu, Wei D.
忆阻器和忆阻器交叉阵列已经被广泛研究用于神经形态和其他存储器内计算应用。然而，为了实现最佳的系统性能，必须将忆阻器交叉开关与外围和控制电路集成。在这里，我们报告了一个功能齐全的，混合忆阻器芯片，其中一个无源交叉阵列直接集成定制设计的电路，包括一套完整的混合信号接口块和一个数字处理器的可重编程计算。忆阻器交叉开关阵列支持在线学习以及向前和向后矢量矩阵运算，而集成接口和控制电路则允许在芯片上映射不同的算法。该系统支持电荷域操作，以通过脉宽调制和定制模数转换器克服忆阻器器件的非线性I-V特性。集成芯片提供了操作神经形态计算硬件所需的所有功能。因此，我们展示了一个感知器网络，稀疏编码算法和主成分分析与集成的分类层使用该系统。
Memristors and memristor crossbar arrays have been widely studied for neuromorphic and other in-memory computing applications. To achieve optimal system performance, however, it is essential to integrate memristor crossbars with peripheral and control circuitry. Here, we report a fully functional, hybrid memristor chip in which a passive crossbar array is directly integrated with custom-designed circuits, including a full set of mixed-signal interface blocks and a digital processor for reprogrammable computing. The memristor crossbar array enables online learning and forward and backward vector-matrix operations, while the integrated interface and control circuitry allow mapping of different algorithms on chip. The system supports charge-domain operation to overcome the nonlinear I-V characteristics of memristor devices through pulse width modulation and custom analogue-to-digital converters. The integrated chip offers all the functions required for operational neuromorphic computing hardware. Accordingly, we demonstrate a perceptron network, sparse coding algorithm and principal component analysis with an integrated classification layer using the system.