Radiation-Hardened Flip-Flops with Small Area and Delay Overheads Using Guard-Gates in FDSOI Processes
Radiation-Hardened Flip-Flops with Small Area and Delay Overheads Using Guard-Gates in FDSOI Processes
复制标题
在 FDSOI 工艺中使用防护门的具有小面积和延迟开销的抗辐射触发器
DOI：
10.1109/s3s.2018.8640212
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发表时间：
2018
期刊：
影响因子：
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通讯作者：
Kazutoshi Kobayashi
中科院分区：
文献类型：
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作者：
Kodai Yamada;J. Furuta;Kazutoshi Kobayashi
在本文中，我们提出了辐射加固触发器（FF）的面积小，延迟短的开销在65纳米的全耗尽绝缘体上硅（FDSOI）工艺。我们设计了两个由保护门组成的FF来消除锁存器中的SET脉冲。虽然额外的晶体管的数量只有两个，建议的FF之一，在CLK =1具有高的软错误容限。虽然附加晶体管的数量为6个，但另一个在CLK =0和1时具有高软错误容限。我们通过器件模拟评估了新设计结构的辐射硬度。模拟结果表明，即使LET为60 MeV-cm 2/mghits的带电粒子，FFS的存储值也不会被打乱。
In this paper we propose radiation-hardened flip-flops (FFs) with small area and short delay overheads in a 65 nm fully depleted silicon on insulator (FDSOI) process. We designed two FFs composed of a guard-gate to eliminate SET pulses in the latch. Although the number of additional transistors is only two, one of the proposed FFs has high soft error tolerance at CLK =1. Although the number of additional transistors is six, the other has high soft error tolerance at CLK =0 and 1. We evaluated the radiation hardness of the newly designed structure by device simulations. Simulation results show that the stored values of the proposed FFs are not upset even though a charged particle with LET of 60 MeV-cm2/mghits.