A Novel Heterogeneous Approximate Multiplier for Low Power and High Performance
A Novel Heterogeneous Approximate Multiplier for Low Power and High Performance
复制标题
一种低功耗高性能的新型异构近似乘法器
DOI：
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发表时间：
2018
影响因子：
1.6
通讯作者：
S. Niar
中科院分区：
文献类型：
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作者：
Ihsen Alouani;Hamzeh Ahangari;O. Ozturk;S. Niar
近似计算是一种设计范例，被考虑用于一系列可以容忍某些精度损失的应用。事实上，传统数字设计技术中的瓶颈可以通过牺牲精度来消除，以实现更高的性能和能效。在这封信中，提出了一种新的架构，从事精度作为设计参数，其中使用异构块的近似并行乘法器实现。基于设计空间探索，我们证明了引入不同的构建块来实现乘法器，而不是克隆一个构建块，可以获得更高的精度结果。我们显示实验结果的精度，延迟和功耗作为指标，并与以前的三个近似设计进行比较。我们的研究结果表明，建议的异构乘法器实现更精确的输出比测试电路，同时提高性能和功耗权衡。
Approximate computing is a design paradigm considered for a range of applications that can tolerate some loss of accuracy. In fact, the bottleneck in conventional digital design techniques can be eliminated to achieve higher performance and energy efficiency by compromising accuracy. In this letter, a new architecture that engages accuracy as a design parameter is presented, where an approximate parallel multiplier using heterogeneous blocks is implemented. Based on design space exploration, we demonstrate that introducing diverse building blocks to implement the multiplier rather than cloning one building block achieves higher precision results. We show experimental results in terms of precision, delay, and power dissipation as metrics and compare with three previous approximate designs. Our results show that the proposed heterogeneous multiplier achieves more precise outputs than the tested circuits while improving performance and power tradeoffs.