A new power-aware FPGA design metric
A new power-aware FPGA design metric
复制标题
一种新的功耗感知 FPGA 设计指标
DOI：
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发表时间：
2015
影响因子：
1.9
通讯作者：
J. Hamlet
中科院分区：
文献类型：
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作者：
Joshua Templin;J. Hamlet
自2001年美国国家标准与技术研究所正式发布高级加密标准以来，已经提出了数十种高级加密标准（AES）实现。这些实现中的许多都针对FPGA平台，用于ASIC原型设计或作为目标硬件。通常，这些出版物都有比较指标，以显示所提出的实现与以前出版的工作相比如何。不幸的是，这些指标往往提供不准确的比较。到目前为止，这些指标都集中在面积和速度上，忽略了硬件优化三角形的第三点，即功耗。随着AES在嵌入式设备中的使用越来越多，越来越有吸引力，电源问题将变得越来越重要。在本文中，我们讨论了以前应用于FPGA AES出版物的度量的微妙之处和质量。然后，我们提出了一个功率度量生成一个更完整的，定量的描述的质量的实施。建议的度量不是特定于AES，但具有一般的FPGA设计适用性。最后，我们提出了四个AES-256实现之间的比较，证明了不一致的结论时，使用各种指标。
Dozens of Advanced Encryption Standard (AES) implementations have been presented since AES was officially published by the National Institute of Standards and Technology in 2001. Many of these implementations have targeted FPGA platforms either for ASIC prototyping or as the destination hardware. Typically, these publications have comparative metrics to show how the proposed implementation compares to previously published work. Unfortunately, these metrics often present inaccurate comparisons. To date, these metrics have focused on area and speed, neglecting the third point of the hardware optimization triangle, power. As AES becomes more prolific and attractive for use in embedded devices, power considerations will be increasingly important. In this paper, we discuss the subtleties and qualities of metrics previously applied to FPGA AES publications. We then propose a power metric to generate a more complete, quantitative description of the quality of the implementation. The proposed metric is not specific to AES but has general FPGA design applicability. Finally, we present a comparison between four AES-256 implementations that demonstrates the inconsistent conclusions drawn when various metrics are used.