New placement prediction and mitigation techniques for local routing congestion

New placement prediction and mitigation techniques for local routing congestion
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针对本地布线拥塞的新布局预测和缓解技术

DOI:
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发表时间:
2010
期刊:
2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)
影响因子:
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通讯作者:
Shyam Ramji
Shyam Ramji
中科院分区:
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文献类型:
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作者:
Taraneh Taghavi;Zhuo Li;C. Alpert;Gi;A. D. Huber;Shyam Ramji

文献摘要

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随着复杂的设计规则使本地引脚访问成为现代设计和路由器的瓶颈,本地路由拥塞变得越来越重要。由于基于全局布线的拥塞分析不能模拟这些影响,可布线性驱动的布局和物理综合不能缓解局部拥塞。这项工作在布局级别对路由拥塞进行建模,以便应用局部拥塞缓解。我们提出了一个局部拥塞度量来计算设计库中每个单元的“路由难度”分数。为了消除局部拥堵,我们应用了一套详细的布局技术,称为MILOR(移动、单元膨胀和合法化,以及行内优化)。实验结果表明,在65纳米、45纳米和32纳米技术的实际工业设计中,我们的技术可以显著提高布线质量。
Local routing congestion is becoming increasingly important as complex design rules make local pin access the bottleneck for modern designs and routers. Since congestion analysis based on global routing does not model these effects, routability-driven placement and physical synthesis fail to alleviate local congestion. This work models routing congestion at the placement level in order to apply local congestion mitigation. We propose a local congestion metric that computes a “routing-difficulty” score for every cell in the design library. To disperse local congestion, we apply a suite of detailed placement techniques called MILOR (Movement, cell Inflation and Legalization, and Optimization within a Row). Experimental results show that our techniques can significantly improve routing quality on real industry designs from 65, 45, and 32 nanometer technologies.