High-Performance Mixed-Signal Neurocomputing With Nanoscale Floating-Gate Memory Cell Arrays
High-Performance Mixed-Signal Neurocomputing With Nanoscale Floating-Gate Memory Cell Arrays
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DOI：
10.1109/tnnls.2017.2778940
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发表时间：
2018-10-01
影响因子：
10.4
通讯作者：
Strukov, Dmitri B.
中科院分区：
文献类型：
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作者：
Merrikh-Bayat, Farnood;Guo, Xinjie;Strukov, Dmitri B.
模拟和混合信号纳米电子电路的潜在优势，基于浮动栅器件可调电导，神经形态计算很久以前就实现了。然而，这种方法的实际实现受到使用相对大面积的基本浮栅单元的影响。在这里，我们报告了一个原型28 × 28二进制输入，十输出，三层神经形态网络的高度优化的嵌入式非易失性浮栅单元阵列的基础上，重新设计的商业180纳米或闪存。电路的所有有源块，包括101 780个浮栅单元，总面积小于1 mm（2）。该网络在常见的美国国家标准与技术研究所基准测试中显示出94.7%的分类保真度，接近模拟中获得的96.2%。一个模式的分类需要一个子1 μ s的时间和一个子20 nJ的能量，这两个数字比在最好的报告数字实现相同的任务。据估计，直接优化硬件并将其转移到现有的55纳米技术可能会将这一优势提高到速度的10（2）倍和能源效率的10（4）倍以上。
Potential advantages of analog-and mixed-signal nanoelectronic circuits, based on floating-gate devices with adjustable conductance, for neuromorphic computing had been realized long time ago. However, practical realizations of this approach suffered from using rudimentary floating-gate cells of relatively large area. Here, we report a prototype 28 x 28 binary-input, ten-output, three-layer neuromorphic network based on arrays of highly optimized embedded nonvolatile floating-gate cells, redesigned from a commercial 180-nm nor flash memory. All active blocks of the circuit, including 101 780 floating-gate cells, have a total area below 1 mm(2). The network has shown a 94.7% classification fidelity on the common Modified National Institute of Standards and Technology benchmark, close to the 96.2% obtained in simulation. The classification of one pattern takes a sub-1-mu s time and a sub-20-nJ energy-both numbers much better than in the best reported digital implementations of the same task. Estimates show that a straightforward optimization of the hardware and its transfer to the already available 55nm technology may increase this advantage to more than 10(2)x in speed and 10(4)x in energy efficiency.