MIRID: Mixed-Mode IR-Drop Induced Delay Simulator
MIRID: Mixed-Mode IR-Drop Induced Delay Simulator
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MIRID：混合模式 IR 压降引起的延迟模拟器
DOI：
10.1109/ats.2013.41
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发表时间：
2013
期刊：
影响因子：
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通讯作者：
I. Polian
中科院分区：
文献类型：
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作者：
Jie Jiang;M. Aparicio;M. Comte;F. Azaïs;M. Renovell;I. Polian
IR-Drop效应在设计和测试环境中都越来越重要。我们介绍了事件驱动的模拟器MIDID，它计算IR-Drop对电路时序的影响。MIDID在两个抽象层次上进行仿真：门级网表中的时序效应和配电网络(PDN)电气模型中的电流和电压波形传播。逻辑门处的开关事件被转发到电气模型，在那里计算感应电流及其对相邻PDN节点的影响。根据该信息，确定在逻辑门的Vdd端子和地端子上的电压值，这些电压值又被用来计算门的准确开关延迟。MIDID支持电气模型的通用接口，允许无缝集成任意模型的PDN和栅极定时。我们报告了基于一个简单的PDN模型的实验，该模型之前已经介绍过，并包含了一个预先表征的库。通过对MIDID和SPICE仿真结果的匹配，验证了仿真的准确性。
IR-drop effects are increasingly relevant in context of both design and test. We introduce the event-driven simulator MIRID that calculates the impact of IR-drop to the circuit timing. MIRID performs the simulation on two abstraction levels: timing effects in the gate-level net-list, current and voltage waveform propagation in the electrical model of the power-distribution network (PDN). Switching events at the logic gates are forwarded to the electrical model, where induced currents and their impact on the neighboring PDN nodes are computed. From this information, values of voltages at the Vdd and ground terminals of logic gates are determined, which in turn are used to calculate accurate switching delays of the gates. MIRID supports a generic interface to electrical models, allowing for a seamless integration of arbitrary models of PDN and gate timing. We report experiments based on a simple PDN model that was introduced previously and incorporates a pre-characterized library. The simulation accuracy is validated by matching the results from MIRID and SPICE.