On broad-side delay test
On broad-side delay test
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DOI:
10.1109/vtest.1994.292299
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发表时间:
1994-04
期刊:
影响因子:
--
通讯作者:
J. Savir;S. Patil
中科院分区:
文献类型:
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作者:
J. Savir;S. Patil
A broad-side delay test is a form of a scan-based delay test, where the first vector of the pair is scanned into the chain, and the second vector of the pair is the combinational circuit's response to this first vector. This delay test form is called "broad-side" since the second vector of the delay test pair is provided in a broad-side fashion, namely through the logic. This paper concentrates on generation of broad-side delay test vectors; shows the results of experiments conducted on the ISCAS sequential benchmarks, and discusses some concerns of the broad-side delay test strategy.>