Design Issues and Considerations for Low-Cost 3-D TSV IC Technology
Design Issues and Considerations for Low-Cost 3-D TSV IC Technology
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DOI：
10.1109/jssc.2010.2074070
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发表时间：
2010-10
影响因子：
5.4
通讯作者：
G. V. D. Plas;P. Limaye;Igor Loi;A. Mercha;H. Oprins;C. Torregiani;S. Thijs;D. Linten;M. Stucchi-M.-Stuc
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文献类型：
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作者：
G. V. D. Plas;P. Limaye;Igor Loi;A. Mercha;H. Oprins;C. Torregiani;S. Thijs;D. Linten;M. Stucchi-M.-Stuc
本文研究了低成本 3D Cu-TSV 技术的关键设计问题和考虑因素。 TSV 对 BEOL 互连可靠性的影响有限，尚未观察到任何故障。 TSV 应力对 MOS 器件的影响会导致偏移，需要进一步分析以了解其重要性。 3D 芯片堆栈中的热热点导致温度升高比 2D 芯片高出三倍，因此需要仔细的热布局规划以避免热故障。我们在 3D 处理过程中监测了 ESD，发现没有发生任何事件，但需要进一步仔细监测。 3D 芯片堆栈中两层之间的噪声耦合比 2D SoC 低 20 dB，为提高混合信号系统性能提供了机会。使用所提出的 RC 模型准确模拟了 TSV 对数字电路性能的影响，并且数字门可以高速、低功耗地直接通过 TSV 驱动信号。 3-D 片上网络实施的实验结果表明，NoC 概念可以以较低的面积 (0.018 ) 和功耗 (3%) 开销从 2-D SoC 扩展到 3-D SoC。
In this paper key design issues and considerations of a low-cost 3-D Cu-TSV technology are investigated. The impact of TSV on BEOL interconnect reliability is limited, no failures have been observed. The impact of TSV stress on MOS devices causes shifts, further analysis is required to understand their importance. Thermal hot spots in 3-D chip stacks cause temperature increases three times higher than in 2-D chips, necessitating a careful thermal floorplanning to avoid thermal failures. We have monitored for ESD during 3-D processing and have found no events take place, however careful further monitoring is required. The noise coupling between two tiers in a 3-D chip-stack is 20 dB lower than in a 2-D SoC, opening opportunities for increased mixed signal system performance. The impact on digital circuit performance of TSVs is accurately modeled with the presented RC model and digital gates can directly drive signals through TSVs at high speed and low power. Experimental results of a 3-D Network-on-Chip implementation demonstrate that the NoC concept can be extended from 2-D SoC to 3-D SoCs at low area (0.018 ) and power (3%) overhead.