A reconfigurable arbiter for SOC applications
A reconfigurable arbiter for SOC applications
复制标题
适用于 SOC 应用的可重构仲裁器
DOI：
--
复制
发表时间：
2008
期刊：
影响因子：
--
通讯作者：
Kai
中科院分区：
文献类型：
--
作者：
Ching;Yu;Shih;Kai
针对SOC通信结构中存在的并发访问冲突问题，提出了一种有效的仲裁算法，并给出了一种基于混合仲裁算法的仲裁器的设计和性能分析。提出了一种静态固定优先级算法与动态优先级算法相结合的混合仲裁算法，以获得更好的系统性能。仿真分析了不同业务负载下各种仲裁算法组合的性能。结果表明，与传统的仲裁分配方案相比，该方案具有更好的性能。在性能分析的基础上，可以对混合仲裁进行自定义调整以满足设计要求。最后，本文还介绍了片上系统应用中仲裁器的混合仲裁方案。可重构仲裁器的FPGA实现和综合的Synopsys设计编译器与台积电0.18妈妈单元库。
For a SOC communication architecture, an efficient arbitration algorithm to resolve contention schemes for managing simultaneous access requests to the shared communication resources are required to prevent system performance degradation.This paper presents the design and performance analysis of an arbiter with a hybrid arbitration algorithm. The hybrid arbitration algorithm contains static fixed priority algorithm in conjunction with dynamic algorithm to gain better system performance is described. The performance analysis for the various combinations of the arbitration algorithms under different traffic loads is simulated. The results indicate a better performance can be achieved as compared with the traditional arbitration assignment scheme. Based on the performance analysis, the hybrid arbitration can be custom-tuned to meet the design requirements. The implementation of the arbiter with hybrid arbitration scheme for system on chip applications is also explained. The reconfigurable arbiter was implemented by FPGA and synthesized by Synopsys design complier with a TSMC 0.18 mum cell library.