Design and implementation of the POWER5/spl trade/ microprocessor
Design and implementation of the POWER5/spl trade/ microprocessor
复制标题
POWER5/spl trade/微处理器的设计与实现
DOI：
10.1109/isscc.2004.1332591
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发表时间：
2004
期刊：
影响因子：
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通讯作者：
S. Dodson
中科院分区：
文献类型：
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作者：
J. Clabes;J. Friedrich;M. Sweet;Jack DiLullo;S. Chu;D. Plass;James Dawson;P. Muench;Larry Powell;Michael Floyd;B. Sinharoy;Mike Lee;Michael Goulet;J. Wagoner;N. Schwartz;S. Runyon;Gary Gorman;P. Restle;R. Kalla;J. McGill;S. Dodson
POWER 5/supTM/是IBM的下一代POWER微处理器。此设计通过整合同步多线程（SMT）、支持164 w SMP的增强型分布式交换机和内存子系统以及广泛的RAS支持，为服务器性能设定了新标准。使用IBM的130纳米绝缘体上硅技术的第一次通过硬件在1.3V下工作在1.5GHz以上。POWER 5的双线程SMT为每个内核创建了最多两个虚拟处理器，从而提高了执行单元的利用率并屏蔽了内存延迟。虽然简单的SMT实现承诺/spl sim/20%的性能改进，但在许多情况下，关键的微架构资源在24%的面积上几乎使SMT性能优势加倍。实现这些微架构增强在满足芯片的频率、面积、功率和热目标方面提出了挑战。
POWER5/sup TM/ is the next generation of IBM's POWER microprocessors. This design, sets a new standard of server performance by incorporating simultaneous multithreading (SMT), an enhanced distributed switch and memory subsystem supporting 164w SMP, and extensive RAS support. First pass hardware using IBM's 130nm silicon-on-insulator technology operates above 1.5GHz at 1.3V. POWER5's dual-threaded SMT creates up to two virtual processors per core, improving execution unit utilization and masking memory latency. Although a simplistic SMT implementation promised /spl sim/20% performance improvement, resizing critical microarchitectural resources almost doubles in many cases the SMT performance benefit at a 24% area. Implementing these microarchitectural enhancements posed challenges in meeting the chip's frequency, area, power, and thermal targets.