Evaluating FPGA clusters under wide ranges of design parameters
Evaluating FPGA clusters under wide ranges of design parameters
复制标题
在各种设计参数下评估 FPGA 集群
DOI：
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发表时间：
2017
期刊：
影响因子：
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通讯作者：
P. Ienne
中科院分区：
文献类型：
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作者：
Grace Zgheib;P. Ienne
最新发表的研究与查找表和集群大小的广泛探索，现在超过十年的历史。然而，CMOS技术以及CAD和晶体管建模工具已经有了很大的改进，因此有理由怀疑这些研究的结论是否仍然成立。进行这些研究的主要困难之一，特别是在学术界，是产生可靠的延迟和面积模型。在本文中，我们利用最近开发的架构建模工具，重新评估的FPGA上的各种集群参数的效果。我们大大扩展了探索空间，超越了经典的研究，包括稀疏的交叉和断裂的LUT，并显示了一些结果，违背了当前的FPGA架构的原则。
The latest published studies with extensive explorations of look-up table and cluster sizes are now more than a decade old. However, CMOS technology as well as CAD and transistor modeling tools have improved so much since that it is reasonable to wonder whether the conclusions of such studies still hold. One of the major difficulties of conducting these studies, especially in academia, is producing credible delay and area models. In this paper, we take advantage of a recently developed architecture modeling tool to re-evaluate the effect of the various cluster parameters on the FPGA. We considerably extend the exploration space beyond that of the classic studies to include sparse crossbars and fracturable LUTs, and show some results that go against the current tenets of FPGA architecture.