Bit Error Tolerance of a CIFAR-10 Binarized Convolutional Neural Network Processor
Bit Error Tolerance of a CIFAR-10 Binarized Convolutional Neural Network Processor
复制标题
CIFAR-10 二值化卷积神经网络处理器的误码容限
DOI：
10.1109/iscas.2018.8351255
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发表时间：
2018
期刊：
影响因子：
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通讯作者：
B. Murmann
中科院分区：
文献类型：
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作者：
Lita Yang;Daniel Bankman;Bert Moons;M. Verhelst;B. Murmann
卷积神经网络（ConvNets）在始终在线的万物互联（IoE）边缘设备中的部署受到硬件卷积神经网络实现的高内存能耗的严重限制。通过在降低电压下接受比特错误来利用卷积神经网络的错误恢复能力，为节能提供了一个可行的选择，但由于对比特错误如何影响性能的定量理解有限，因此很少有实现使用这种方法。本文证明了SRAM电压缩放在9层CIFAR-10二值化ConvNet处理器中的有效性，实现了3.12倍的存储能量节约，精度下降最小（标称的99%）。此外，我们量化了多层网络中误码积累的影响，并表明通过拆分权重和激活电压可以进一步节省能源。最后，我们比较了CIFAR-10二值化卷积神经网络与MNIST网络的误码率，以展示在网络拓扑和分类任务的不同复杂性下误码率要求的差异。
Deployment of convolutional neural networks (ConvNets) in always-on Internet of Everything (IoE) edge devices is severely constrained by the high memory energy consumption of hardware ConvNet implementations. Leveraging the error resilience of ConvNets by accepting bit errors at reduced voltages presents a viable option for energy savings, but few implementations utilize this due to the limited quantitative understanding of how bit errors affect performance. This paper demonstrates the efficacy of SRAM voltage scaling in a 9-layer CIFAR-10 binarized ConvNet processor, achieving memory energy savings of 3.12× with minimal accuracy degradation (∼99% of nominal). Additionally, we quantify the effect of bit error accumulation in a multi-layer network and show that further energy savings are possible by splitting weight and activation voltages. Finally, we compare the measured error rates for the CIFAR-10 binarized ConvNet against MNIST networks to demonstrate the difference in bit error requirements across varying complexity in network topologies and classification tasks.