Upset hardened memory design for submicron CMOS technology
Upset hardened memory design for submicron CMOS technology
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DOI:
10.1109/23.556880
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发表时间:
1996-12-01
影响因子:
1.8
通讯作者:
Velazco, R
中科院分区:
文献类型:
--
作者:
Calin, T;Nicolaidis, M;Velazco, R
A novel design technique is proposed for storage elements which are insensitive to radiation-induced single-event upsets. This technique is suitable for implementation in high density ASICs and static RAMs using submicron CMOS technology.