Continuous-flow Parallel Bit-Reversal Circuit for MDF and MDC FFT Architectures
Continuous-flow Parallel Bit-Reversal Circuit for MDF and MDC FFT Architectures
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适用于 MDF 和 MDC FFT 架构的连续流并行位反转电路
DOI：
10.1109/tcsi.2014.2327271
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发表时间：
2014
期刊：
影响因子：
--
通讯作者：
S. Jou
中科院分区：
文献类型：
--
作者：
Sau;Shen;M. Garrido;S. Jou
本文提出了一种用于连续流并行流水线 FFT 处理器的位反转电路。除了两个灵活的换向器外，该电路还由两个存储器组组成，每个组有P个存储器组。考虑到同时实现低延迟时间和区域复杂度，设计了一种新颖的写/读调度机制，使得FFT输出可以以优化的方式存储在这些存储体中。所提出的调度机制可以在当前连续生成的FFT输出数据样本被前一个符号连续释放后立即将其无任何延迟地写入到这些位置。因此，仅N个数据样本的总存储空间就足以进行连续流FFT运算。由于在整个周期内读操作与写操作不重叠，因此只需要单端口存储器，这导致面积大大减少。所提出的位反转电路架构可以生成自然阶 FFT 输出并支持可变的 2 次方 FFT 长度。
This paper presents a bit reversal circuit for continuous-flow parallel pipelined FFT processors. In addition to two flexible commutators, the circuit consists of two memory groups, where each group has P memory banks. For the consideration of achieving both low delay time and area complexity, a novel write/read scheduling mechanism is devised, so that FFT outputs can be stored in those memory banks in an optimized way. The proposed scheduling mechanism can write the current successively generated FFT output data samples to the locations without any delay right after they are successively released by the previous symbol. Therefore, total memory space of only N data samples is enough for continuous-flow FFT operations. Since read operation is not overlapped with write operation during the entire period, only single-port memory is required, which leads to great area reduction. The proposed bit-reversal circuit architecture can generate natural-order FFT output and support variable power-of-2 FFT lengths.